An FPGA-Based Doppler Processor for a Spaceborne Precipitation Radar

S. L. Durden Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California

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M. A. Fischman Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California

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R. A. Johnson Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California

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A. J. Chu Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California

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M. N. Jourdan Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California

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S. Tanelli Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California

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Abstract

Measurement of precipitation Doppler velocity by spaceborne radar is complicated by the large velocity of the satellite platform. Even if successive pulses are well correlated, the velocity measurement may be biased if the precipitation target does not uniformly fill the radar footprint. It has been previously shown that the bias in such situations can be reduced if full spectral processing is used. The authors present a processor based on field-programmable gate array (FPGA) technology that can be used for spectral processing of data acquired by future spaceborne precipitation radars. The requirements for and design of the Doppler processor are addressed. Simulation and laboratory test results show that the processor can meet real-time constraints while easily fitting in a single FPGA.

Corresponding author address: S. L. Durden, JPL MS 300-243, 4800 Oak Grove Dr., Pasadena, CA 91109. Email: sdurden@jpl.nasa.gov

Abstract

Measurement of precipitation Doppler velocity by spaceborne radar is complicated by the large velocity of the satellite platform. Even if successive pulses are well correlated, the velocity measurement may be biased if the precipitation target does not uniformly fill the radar footprint. It has been previously shown that the bias in such situations can be reduced if full spectral processing is used. The authors present a processor based on field-programmable gate array (FPGA) technology that can be used for spectral processing of data acquired by future spaceborne precipitation radars. The requirements for and design of the Doppler processor are addressed. Simulation and laboratory test results show that the processor can meet real-time constraints while easily fitting in a single FPGA.

Corresponding author address: S. L. Durden, JPL MS 300-243, 4800 Oak Grove Dr., Pasadena, CA 91109. Email: sdurden@jpl.nasa.gov

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